1. Field of the Invention
Embodiments of the present invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to semiconductor memory devices comprising floating body memory cells.
2. Description of Related Art
Researchers continue to seek new ways of increasing the integration density and performance of semiconductor memory cell arrays. One recent proposal for creating smaller memory cell arrays focuses on replacing conventional dynamic random access memory (DRAM) cells with so-called “floating body memory cells”.
In a floating body memory cell, electrical charges are stored in a floating body of a floating body transistor. However, charges tend to leak out of the floating body over time and therefore the floating body transistor must be periodically refreshed. In this respect, floating body memory cells are similar to DRAM cells, which also must be periodically refreshed. However, because floating body transistors do not require both a storage capacitor and an access transistor, as DRAM cells do, floating body transistors tend to be smaller than DRAM cells.
Figure (FIG.) 1 is a schematic diagram of a conventional semiconductor memory device comprising floating body memory cells.
Referring to FIG. 1, the conventional semiconductor memory device comprises memory cell array blocks BLK1 and BLK2, bit line selectors 10-11 through 10-1m and 10-21 through 10-2m, reference bit line selectors 12-1 and 12-2, level limiters 14-1 through 14-m, and 14-(m+1), sense amplifiers 16-1 through 16-m, a reference voltage generator 18, comparators COM1 through COMm, latches LA1 through LAm, write back gates WBG1 through WBGm, read column selection gates RG1 through RGm, write column selection gates WG1 through WGm, and a reference write column selection gate RWG.
Memory cell array blocks BLK1 and BLK2 comprise respective sub-memory cell array blocks SBLK11 through SBLK1m and SBLK21 through SBLK2m each comprising storage memory cells, and reference memory cell array blocks RBLK1 and RBLK2 each comprising reference memory cells. Write and read operations of the storage memory cells and the reference memory cells will be described in further detail below. For explanation purposes, the operation of a reference memory cell labeled RMC will be described. Other reference memory cells function similar to reference memory cell RMC. Similarly, the operation of a storage memory cell MC will be described. Other storage memory cells function similar to storage memory cell MC.
In a write operation for writing data in reference memory cell RMC, a word line WL11 is enabled by applying a voltage of about 1.5 V thereto, and reference bit line selection signal RBS1 is enabled. As a result, a reference bit line RBL1 is connected to a reference sense bit line RSBL. A reference write column selection signal RWCSL is enabled, and a N-channel metal-oxide semiconductor (NMOS) transistor N7 is turned on so that write data apparent on a write data line WD is transmitted through reference sense bit line RSBL to reference bit line RBL1. Where the write data on write data line WD has a voltage level of about −1.5 V, data “0” is written to reference memory cell RMC connected between the word line WL11 and reference bit line RBL1. By similar operations, data “0” can be written to reference memory cells connected between the remaining word lines WL12 through WL1n and reference bit line RBL1.
Similarly, data “1” can be written to reference memory cells connected between word lines WL11 through WL1n and WL21 through WL2n and a reference bit line RBL2 by applying a voltage of about 1.5 V to write data line WD.
In other words, data “0” is written to reference memory cells connected to reference bit line RBL1 within each of reference memory cell array blocks RBLK1 and RBLK2, while data “1” is written to reference memory cells connected to reference bit line RBL2 within each of reference memory cell array blocks RBLK1 and RBLK2. The data stored in the reference memory cells is used to generate a reference voltage VRED for read operations of storage memory cells.
In a write operation of storage memory cell MC, a voltage of about 1.5 V is applied to word line WL11, and a bit line selection signal BS1 is enabled. As a result, a bit line BL1 is connected to a sense bit line SBL1. Where a write column selection signal WCSL1 is enabled, an NMOS transistor N6 is turned on. At this time, when a voltage of about −1.5 V is applied to write data line WD, the voltage of about −1.5V is transmitted through sense bit line SBL1 to bit line BL1, so that data “0” is written to storage memory cell MC connected between word line WL1 and bit line BL1.
On the other hand, where a voltage of about 1.5 V is applied to write data line WD, data “1” is written to storage memory cell MC connected between word line WL1 and bit line BL1. Using similar operations, data can be written to all storage memory cells in memory cell array blocks BLK1 and BLK2.
In a read operation of storage memory cell MC, a voltage of about 1.5 V is applied to word line WL11 and bit line selection signal BS1 is enabled. As a result, bit line BL1 is connected to sense bit line SBL1 and a signal is transmitted from bit line BL1 to sense bit line SBL1. Here, reference bit line selection signals RBS1 and RBS2 are concurrently enabled, and thus reference bit lines RBL1 and RBL2 are connected to reference sense bit line RSBL, and a signal is transmitted from reference bit lines RBL1 and RBL2 to reference sense bit line RSBL.
Where a voltage level of sense bit line SBL1 due to a current supplied to sense bit line SBL1 is at a higher level than a restricted voltage VBLR, level limiter 14-1 prevents the flow of current from its output node a1 to sense bit line SBL1 such that the voltage level of sense bit line SBL1 remains below the level of restricted voltage VBLR, and generates a current Ic1 corresponding to data stored in storage memory cell MC.
Where a voltage level of reference sense bit line RSBL is higher than restricted voltage VBLR due to a current supplied to reference sense bit line RSBL, level limiter 14-(m+1) prevents the flow of current from its output node a(m+1) to the reference sense bit line RSBL such that the voltage level of reference sense bit line RSBL remains below the level of restricted voltage VBLR, and generates a current Ic(m+1) corresponding to data stored in reference memory cell RMC.
Sense amplifier 16-1 senses current Ic1 and generates a sensing voltage Sn1. Reference voltage generator 18 senses current Ic(m+1) and generates a reference voltage VREF. Comparator COM1 is enabled in response to a sense amplifier enable signal SEN, compares the sensing voltage output from sense amplifier 16-1 with reference voltage VREF and generates sensing data. Specifically, comparator COM1 outputs a high-level signal to a corresponding node “a”, when sensing voltage Sn1 output from sense amplifier 16-1 is at a lower level than reference voltage VREF, and outputs a low-level signal to the corresponding node “a” when sensing voltage Sn1 is at a higher level than reference voltage VREF.
Latch LA1 latches data apparent at node “a”, and when a read column selection signal RCSL1 is enabled, NMOS transistors N2 and N4 are turned on. At this time, where a voltage at the node “a” is at a high level, an NMOS transistor N5 is turned on and transmits low-level data to an inverted read data line RDB. On the other hand, where a voltage at a node “b” is at a high level, an NMOS transistor N3 is turned on and transmits low-level data to a read data line RD. In other words, low-level data is transmitted to read data line RD or inverted read data line RDB during a read operation. After the read operation is finished, a write back signal WB is enabled and an NMOS transistor N1 is turned on. Consequently, high-level data apparent at node “b” of latch LA1 is transmitted to sense bit line SBL1, and data in sense bit line SBL1 is transmitted to bit line BL1. As a result, a refresh operation is performed on storage memory cell MC connected between word line WL11 and bit line BL1 and having data “1” stored therein. Using a similar process, read operations can be performed on other storage memory cells in memory cell array blocks BLK1 and BLK2.
An example of the conventional semiconductor memory device shown in FIG. 1 is described in further detail in U.S. Patent Application Publication No. 2003/0231524. Other examples of semiconductor memory devices including memory cells and reference memory cells having floating bodies are disclosed in U.S. Patent Application Publication No. 2005/0068807 and U.S. Pat. Nos. 6,567,330 and 6,882,008.
As described above, the conventional semiconductor memory device shown in FIG. 1 includes reference memory cells storing data “0” and reference memory cells storing data “1” for performing read operations. The semiconductor memory device of FIG. 1 typically includes a single reference memory cell array block for each memory cell array block. However, the semiconductor memory device could include a reference memory cell array block for a predetermined number of sub-memory cell array blocks within each memory cell array block.
Although the conventional semiconductor memory device of FIG. 1 is designed so that reference memory cells and storage memory cells permit the flow of current corresponding to data “0” when the data “0” is read, and permit the flow of current corresponding to data “1” when the data “1” is read, the currents corresponding to the data “0” and “1” vary according to changes in fabrication process, voltage, and temperature. Unfortunately, this variance in current may result in read errors. For example, data “0” stored in memory cell MC could be read as data “1”, or data “1” stored in memory cell MC could be read as data “0”. Such errors result from erroneous comparisons between currents on the bit line and the reference bit line during data read operations.
In addition to the potential read errors, the conventional semiconductor memory device of FIG. 1 also requires a complicated circuit configuration for read operations. For example, the conventional semiconductor memory device requires a level limiter, a sense amplifier, a comparator, and a latch as shown in FIG. 1.
Moreover, in the conventional semiconductor memory device shown in FIG. 1, a negative voltage of −1.5 V is applied to the bit line to write data “0”. Accordingly, the conventional semiconductor memory device needs a negative voltage generator for generating a negative voltage to be applied to the bit line when writing data “0”.